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Recent advances in virtualization technologies used in cloud computing offer performance that closely approaches bare-metal levels. Combined with specialized instance types and high-speed networking services for cluster computing, cloud platforms have become a compelling option for high-performance computing (HPC). However, most current batch job schedulers in HPC systems are designed for homogeneous clusters and make decisions based on limited information about jobs and system status. Scientists typically submit computational jobs to these schedulers with a requested runtime that is often over- or under-estimated. More accurate runtime predictions can help schedulers make better decisions and reduce job turnaround times. They can also support decisions about migrating jobs to the cloud to avoid long queue wait times in HPC systems. In this study, we design neural network models to predict the runtime and resource utilization of jobs on integrated cloud and HPC systems. We developed two monitoring strategies to collect job and system resource utilization data using a workload management system and a cloud monitoring service. We evaluated our models on two Department of Energy (DOE) HPC systems and Amazon Web Services (AWS). Our results show that we can predict the runtime of a job with 31–41 % mean absolute percentage error (MAPE), 14–17 seconds mean absolute value error (MAE), and 0.99 R-squared (R²) score. Having an MAE of less than a minute corresponds to 100 % accuracy since the requested time for batch jobs is always specified in hours and/or minutesmore » « lessFree, publicly-accessible full text available March 1, 2027
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Free, publicly-accessible full text available September 1, 2026
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Free, publicly-accessible full text available September 1, 2026
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It has recently been shown that emerging frequency selective limiter (FSL) devices allow to suppress interference with high power levels in the same frequency band as desired signals. This paper introduces an FSL model for circuit simulations that was validated with measurement results of a prototype FSL device. An RF front-end was constructed with this FSL model and a transistor-level CMOS low-noise amplifier (LNA) design. A co-simulation methodology has been developed under large-signal interference considerations using the Bluetooth Low-Energy (BLE) standard as a representative example. Results from simulations with a two-tone signal confirm that the modeled FSL can provide a 9.4 dB reduction of the third-order intermodulation distortion (IMD3) components, which benefits resilience to interference.more » « lessFree, publicly-accessible full text available October 9, 2026
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Free, publicly-accessible full text available August 16, 2026
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Free, publicly-accessible full text available September 1, 2026
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Free, publicly-accessible full text available September 1, 2026
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Free, publicly-accessible full text available May 21, 2026
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Free, publicly-accessible full text available June 23, 2026
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Free, publicly-accessible full text available June 2, 2026
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